From 4c3cc72cc7760f2aa3411e1e0f1a6cfca2659653 Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Thu, 4 Apr 2013 13:32:43 +0900 Subject: [PATCH] clk: exynos4: Add missing mout_mipihsi clock This patch adds missing output of mux MIPIHSI which is needed for div_mipihsi clock. Signed-off-by: Tomasz Figa Signed-off-by: Kyungmin Park Reviewed-by: Thomas Abraham Acked-by: Mike Turquette Signed-off-by: Kukjin Kim --- drivers/clk/samsung/clk-exynos4.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 8edd64cb18a8..42c098df2e22 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -381,6 +381,7 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = { MUX(none, "mout_mmc2", group1_p4x12, SRC_FSYS, 8, 4), MUX(none, "mout_mmc3", group1_p4x12, SRC_FSYS, 12, 4), MUX(none, "mout_mmc4", group1_p4x12, SRC_FSYS, 16, 4), + MUX(none, "mout_mipihsi", aclk_p4412, SRC_FSYS, 24, 1), MUX(none, "mout_uart0", group1_p4x12, SRC_PERIL0, 0, 4), MUX(none, "mout_uart1", group1_p4x12, SRC_PERIL0, 4, 4), MUX(none, "mout_uart2", group1_p4x12, SRC_PERIL0, 8, 4), -- 2.30.2