From 8e504bccc11663c3b334ef1a7698e18a967de920 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 17 Nov 2017 10:44:15 -0500 Subject: [PATCH] drm/amd/display: Disable plane right after disconnected HDR display playing video underflow is observed when switching to full screen due to program a lower watermark right after unlock otg. Instead of disable plane in next flip coming, if there is a plane disconnected, after otg unlock wait for mpcc idle and disable the plane, then program watermark. So there is enough warter mark to make sure current frame data pass through. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 1ebe980bfb6d..d542e4db5495 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2297,7 +2297,7 @@ static void dcn10_apply_ctx_for_surface( pipe_ctx->plane_state->update_flags.bits.full_update) program_water_mark = true; - if (removed_pipe[i] && num_planes == 0) + if (removed_pipe[i]) dcn10_disable_plane(dc, old_pipe_ctx); } @@ -2306,6 +2306,7 @@ static void dcn10_apply_ctx_for_surface( /* pstate stuck check after watermark update */ dcn10_verify_allow_pstate_change_high(dc); } + /* watermark is for all pipes */ hubbub1_program_watermarks(dc->res_pool->hubbub, &context->bw.dcn.watermarks, ref_clk_mhz); -- 2.30.2