From 94997e041b96a37072942d8a8745b6db433db552 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Sun, 25 Nov 2012 16:38:16 +0000 Subject: [PATCH] brcm47xx: fix cpu clock detection on ASUS WL-520gU The ASUS WL-520gU and some other similar Asus devices have a BCM5354 running at 200MHZ and not at 240 which is the default for this SoC. This fixes #4083. Backport of r34325. SVN-Revision: 34377 --- ...-time-for-WL520G-and-other-200-MHz-C.patch | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 target/linux/brcm47xx/patches-3.3/520-MIPS-BCM47XX-fix-time-for-WL520G-and-other-200-MHz-C.patch diff --git a/target/linux/brcm47xx/patches-3.3/520-MIPS-BCM47XX-fix-time-for-WL520G-and-other-200-MHz-C.patch b/target/linux/brcm47xx/patches-3.3/520-MIPS-BCM47XX-fix-time-for-WL520G-and-other-200-MHz-C.patch new file mode 100644 index 0000000000..2ae45e8f44 --- /dev/null +++ b/target/linux/brcm47xx/patches-3.3/520-MIPS-BCM47XX-fix-time-for-WL520G-and-other-200-MHz-C.patch @@ -0,0 +1,44 @@ +--- a/arch/mips/bcm47xx/time.c ++++ b/arch/mips/bcm47xx/time.c +@@ -27,10 +27,14 @@ + #include + #include + #include ++#include + + void __init plat_time_init(void) + { + unsigned long hz = 0; ++ u16 chip_id = 0; ++ char buf[10]; ++ int len; + + /* + * Use deterministic values for initial counter interrupt +@@ -43,15 +47,26 @@ void __init plat_time_init(void) + #ifdef CONFIG_BCM47XX_SSB + case BCM47XX_BUS_TYPE_SSB: + hz = ssb_cpu_clock(&bcm47xx_bus.ssb.mipscore) / 2; ++ chip_id = bcm47xx_bus.ssb.chip_id; + break; + #endif + #ifdef CONFIG_BCM47XX_BCMA + case BCM47XX_BUS_TYPE_BCMA: + hz = bcma_cpu_clock(&bcm47xx_bus.bcma.bus.drv_mips) / 2; ++ chip_id = bcm47xx_bus.bcma.bus.chipinfo.id; + break; + #endif + } + ++ if (chip_id == 0x5354) { ++ len = nvram_getenv("clkfreq", buf, sizeof(buf)); ++ if (len >= 0 && !strncmp(buf, "200", 4)) ++ hz = 100000000; ++ len = nvram_getenv("hardware_version", buf, sizeof(buf)); ++ if (len >= 0 && !strncmp(buf, "WL520G", 6)) ++ hz = 100000000; ++ ++ } + if (!hz) + hz = 100000000; + -- 2.30.2