From 98df6d5b877c26012bbafcf07ff51326db4ef3f7 Mon Sep 17 00:00:00 2001 From: Tariq Toukan Date: Sun, 16 Dec 2018 17:20:31 +0200 Subject: [PATCH] net/mlx5: A write memory barrier is sufficient in EQ ci update Soften the memory barrier call of mb() by a sufficient wmb() in the consumer index update of the event queues. Signed-off-by: Tariq Toukan Signed-off-by: Saeed Mahameed --- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eq.c b/drivers/net/ethernet/mellanox/mlx5/core/eq.c index 46a747f7c162..e9837aeb7088 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eq.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eq.c @@ -707,7 +707,7 @@ void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm) __raw_writel((__force u32)cpu_to_be32(val), addr); /* We still want ordering, just not swabbing, so add a barrier */ - mb(); + wmb(); } EXPORT_SYMBOL(mlx5_eq_update_ci); -- 2.30.2