From 9918271efc7ab9e5efc9580270f67c126901b06f Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Mon, 11 Apr 2016 16:56:25 +0300 Subject: [PATCH] drm/i915: Skip display irq setup if display irqs aren't flagged as enabled MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit During runtime PM we'll be reinitializing interrupt support from the ground up. However since the display power well will be off at that time, well end up with a ton of unclaimed register accesses from the display irq setup. Since we turned off the power well already before runtime suspend, we've flagged display irqs as disabled during runtime PM transitions. So we can just check that flag to see if we should do skip display irqs during irq setup. During driver load display irqs will be flagged as enabled since we've turned on the power well already, however the power well code will have skipped the display irq setup since irq support as a whole wasn't yet enabled when the power well was enabled. So we'll want to do the display irq setup in that case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94164 Signed-off-by: Ville Syrjälä Link: http://patchwork.freedesktop.org/patch/msgid/1460382992-28728-4-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/i915_irq.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 0fcd8b24a1de..68981aee35b7 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3329,7 +3329,8 @@ static void valleyview_irq_preinstall(struct drm_device *dev) I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } @@ -3406,7 +3407,8 @@ static void cherryview_irq_preinstall(struct drm_device *dev) I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } @@ -3728,7 +3730,8 @@ static int valleyview_irq_postinstall(struct drm_device *dev) #endif spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_postinstall(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_postinstall(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); @@ -3834,7 +3837,8 @@ static int cherryview_irq_postinstall(struct drm_device *dev) gen8_gt_irq_postinstall(dev_priv); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_postinstall(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_postinstall(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); @@ -3867,7 +3871,8 @@ static void valleyview_irq_uninstall(struct drm_device *dev) I915_WRITE(HWSTAM, 0xffffffff); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } @@ -3886,7 +3891,8 @@ static void cherryview_irq_uninstall(struct drm_device *dev) GEN5_IRQ_RESET(GEN8_PCU_); spin_lock_irq(&dev_priv->irq_lock); - vlv_display_irq_reset(dev_priv); + if (dev_priv->display_irqs_enabled) + vlv_display_irq_reset(dev_priv); spin_unlock_irq(&dev_priv->irq_lock); } -- 2.30.2