From 9fb4bfd0be010371d3fdd2280e9d99f315382379 Mon Sep 17 00:00:00 2001 From: Sharat Masetty Date: Thu, 27 Sep 2018 22:16:22 +0530 Subject: [PATCH] drm/msm/a6xx: Send the right perf index value to GMU The index of the perf table was being set in the wrong bit position in the register. With this fix, the GPU clock can be seen running at desired frequency. Signed-off-by: Sharat Masetty Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index bbb8126ec5c5..bfa3f468a31c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -70,7 +70,7 @@ static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, - ((index << 24) & 0xff) | (3 & 0xf)); + ((3 & 0xf) << 28) | index); /* * Send an invalid index as a vote for the bus bandwidth and let the -- 2.30.2