From b6241002039118d6bea78f50f8f19195b41ab602 Mon Sep 17 00:00:00 2001 From: Yan Zhao Date: Tue, 7 May 2019 22:16:33 -0400 Subject: [PATCH] drm/i915/gvt: add 0x4dfc to gen9 save-restore list 0x4dfc is in-context mmio for gen9+, but each vm have different settings need to add it to save-restore list along with other trtt registers Fixes: 178657139307 ("drm/i915/gvt: vGPU context switch") Acked-by: Zhenyu Wang Signed-off-by: Yan Zhao Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/mmio_context.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/gvt/mmio_context.c b/drivers/gpu/drm/i915/gvt/mmio_context.c index f4e60d736cfb..90bb3df0db50 100644 --- a/drivers/gpu/drm/i915/gvt/mmio_context.c +++ b/drivers/gpu/drm/i915/gvt/mmio_context.c @@ -114,6 +114,7 @@ static struct engine_mmio gen9_engine_mmio_list[] __cacheline_aligned = { {RCS0, TRINVTILEDETCT, 0, true}, /* 0x4dec */ {RCS0, TRVADR, 0, true}, /* 0x4df0 */ {RCS0, TRTTE, 0, true}, /* 0x4df4 */ + {RCS0, _MMIO(0x4dfc), 0, true}, {BCS0, RING_GFX_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2229c */ {BCS0, RING_MI_MODE(BLT_RING_BASE), 0xffff, false}, /* 0x2209c */ -- 2.30.2