From b6b41cf3b64f88472f08276a90248a6fa36ee8c7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 7 Nov 2014 13:24:54 -0500 Subject: [PATCH] drm/radeon: fix default dpm state setup Only enable the first levels for mclk and sclk. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ci_dpm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index aad64770ee55..dbc6d2aa6d22 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -3062,19 +3062,21 @@ static int ci_setup_default_dpm_tables(struct radeon_device *rdev) allowed_sclk_vddc_table->entries[i].clk)) { pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = allowed_sclk_vddc_table->entries[i].clk; - pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true; + pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = + (i == 0) ? true : false; pi->dpm_table.sclk_table.count++; } } pi->dpm_table.mclk_table.count = 0; for (i = 0; i < allowed_mclk_table->count; i++) { - if ((i==0) || + if ((i == 0) || (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != allowed_mclk_table->entries[i].clk)) { pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = allowed_mclk_table->entries[i].clk; - pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true; + pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = + (i == 0) ? true : false; pi->dpm_table.mclk_table.count++; } } -- 2.30.2