From c15c8d70207d467bb4312d6ac5536c101246fdc6 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Wed, 6 Jan 2016 16:48:38 +0800 Subject: [PATCH] drm/amd/powerplay: fix Smatch static checker warnings 1. return -1 instead of -ENOMEM 2. The struct type mismatch warnings. Signed-off-by: Rex Zhu Reviewed-by: Alex Deucher Reviewed-by: Ken Wang Signed-off-by: Alex Deucher --- .../gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c | 2 +- .../drm/amd/powerplay/hwmgr/functiontables.c | 13 ++++---- drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 3 ++ .../drm/amd/powerplay/hwmgr/processpptables.c | 11 ++++++- .../gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c | 30 +++++++++++-------- .../powerplay/hwmgr/tonga_processpptables.c | 20 ++++++------- .../drm/amd/powerplay/smumgr/fiji_smumgr.c | 2 +- .../drm/amd/powerplay/smumgr/tonga_smumgr.c | 2 +- 8 files changed, 51 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c index 6dba5bf73e52..3f3009d6b6e0 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c @@ -914,7 +914,7 @@ static int fiji_trim_voltage_table(struct pp_hwmgr *hwmgr, GFP_KERNEL); if (NULL == table) - return -EINVAL; + return -ENOMEM; table->mask_low = vol_table->mask_low; table->phase_delay = vol_table->phase_delay; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c index 5abde8f6d108..9deadabbc81c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c @@ -66,7 +66,7 @@ int phm_dispatch_table(struct pp_hwmgr *hwmgr, temp_storage = kzalloc(rt_table->storage_size, GFP_KERNEL); if (temp_storage == NULL) { printk(KERN_ERR "[ powerplay ] Could not allocate table temporary storage\n"); - return -1; + return -ENOMEM; } } @@ -90,7 +90,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr, if (hwmgr == NULL || master_table == NULL || rt_table == NULL) { printk(KERN_ERR "[ powerplay ] Invalid Parameter!\n"); - return -1; + return -EINVAL; } for (table_item = master_table->master_list; @@ -102,8 +102,9 @@ int phm_construct_table(struct pp_hwmgr *hwmgr, size = (function_count + 1) * sizeof(phm_table_function); run_time_list = kzalloc(size, GFP_KERNEL); + if (NULL == run_time_list) - return -1; + return -ENOMEM; rtf = run_time_list; for (table_item = master_table->master_list; @@ -111,7 +112,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr, if ((rtf - run_time_list) > function_count) { printk(KERN_ERR "[ powerplay ] Check function results have changed\n"); kfree(run_time_list); - return -1; + return -EINVAL; } if ((NULL == table_item->isFunctionNeededInRuntimeTable) || @@ -123,7 +124,7 @@ int phm_construct_table(struct pp_hwmgr *hwmgr, if ((rtf - run_time_list) > function_count) { printk(KERN_ERR "[ powerplay ] Check function results have changed\n"); kfree(run_time_list); - return -1; + return -EINVAL; } *rtf = NULL; @@ -138,7 +139,7 @@ int phm_destroy_table(struct pp_hwmgr *hwmgr, { if (hwmgr == NULL || rt_table == NULL) { printk(KERN_ERR "[ powerplay ] Invalid Parameter\n"); - return -1; + return -EINVAL; } if (NULL == rt_table->function_list) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index ca4554b402f9..5fb98aa2e719 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -111,6 +111,9 @@ int hw_init_power_state_table(struct pp_hwmgr *hwmgr) hwmgr->ps = kzalloc(size * table_entries, GFP_KERNEL); + if (hwmgr->ps == NULL) + return -ENOMEM; + state = hwmgr->ps; for (i = 0; i < table_entries; i++) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c index 8f9d705bbde2..2f1a14fe05b1 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c @@ -1322,11 +1322,17 @@ static int get_cac_leakage_table(struct pp_hwmgr *hwmgr, struct phm_cac_leakage_table *cac_leakage_table; unsigned long table_size, i; + if (hwmgr == NULL || table == NULL || ptable == NULL) + return -EINVAL; + table_size = sizeof(ULONG) + (sizeof(struct phm_cac_leakage_table) * table->ucNumEntries); cac_leakage_table = kzalloc(table_size, GFP_KERNEL); + if (cac_leakage_table == NULL) + return -ENOMEM; + cac_leakage_table->count = (ULONG)table->ucNumEntries; for (i = 0; i < cac_leakage_table->count; i++) { @@ -1349,7 +1355,7 @@ static int get_cac_leakage_table(struct pp_hwmgr *hwmgr, static int get_platform_power_management_table(struct pp_hwmgr *hwmgr, ATOM_PPLIB_PPM_Table *atom_ppm_table) { - struct phm_ppm_table *ptr = kzalloc(sizeof(ATOM_PPLIB_PPM_Table), GFP_KERNEL); + struct phm_ppm_table *ptr = kzalloc(sizeof(struct phm_ppm_table), GFP_KERNEL); if (NULL == ptr) return -ENOMEM; @@ -1466,6 +1472,9 @@ static int init_phase_shedding_table(struct pp_hwmgr *hwmgr, table = kzalloc(size, GFP_KERNEL); + if (table == NULL) + return -ENOMEM; + table->count = (unsigned long)ptable->ucNumEntries; for (i = 0; i < table->count; i++) { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c index 3cb5d041b3cf..0b188d13364f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c @@ -115,9 +115,12 @@ const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic); struct tonga_power_state *cast_phw_tonga_power_state( struct pp_hw_power_state *hw_ps) { + if (hw_ps == NULL) + return NULL; + PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), "Invalid Powerstate Type!", - return NULL;); + return NULL); return (struct tonga_power_state *)hw_ps; } @@ -125,9 +128,12 @@ struct tonga_power_state *cast_phw_tonga_power_state( const struct tonga_power_state *cast_const_phw_tonga_power_state( const struct pp_hw_power_state *hw_ps) { + if (hw_ps == NULL) + return NULL; + PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic), "Invalid Powerstate Type!", - return NULL;); + return NULL); return (const struct tonga_power_state *)hw_ps; } @@ -1678,9 +1684,9 @@ static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency); CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency); //CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage); - } + } - return result; + return result; } @@ -1719,7 +1725,7 @@ static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr, PP_ASSERT_WITH_CODE((0 == result), "can not find divide id for VCE engine clock", return result); - table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider; CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency); } @@ -1804,7 +1810,7 @@ static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr, PP_ASSERT_WITH_CODE((0 == result), "can not find divide id for samu clock", return result); - table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; + table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider; CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency); } @@ -1847,7 +1853,7 @@ static int tonga_calculate_mclk_params( "Error retrieving Memory Clock Parameters from VBIOS.", return result); /* MPLL_FUNC_CNTL setup*/ - mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); + mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl); /* MPLL_FUNC_CNTL_1 setup*/ mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1, @@ -3864,6 +3870,7 @@ int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table, phw_to table->mc_reg_table_entry[i].mc_data[j]; } } + ni_table->num_entries = table->num_entries; return 0; @@ -3989,7 +3996,7 @@ int tonga_initialize_mc_reg_table(struct pp_hwmgr *hwmgr) table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL); if (NULL == table) - return -1; + return -ENOMEM; /* Program additional LP registers that are no longer programmed by VBIOS */ cgs_write_register(hwmgr->device, mmMC_SEQ_RAS_TIMING_LP, cgs_read_register(hwmgr->device, mmMC_SEQ_RAS_TIMING)); @@ -5470,7 +5477,6 @@ static int tonga_generate_dpm_level_enable_mask(struct pp_hwmgr *hwmgr, const vo struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend); const struct tonga_power_state *tonga_ps = cast_const_phw_tonga_power_state(states->pnew_state); - result = tonga_trim_dpm_states(hwmgr, tonga_ps); if (0 != result) return result; @@ -5732,7 +5738,7 @@ static int tonga_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_ if (phm_is_hw_access_blocked(hwmgr)) return 0; - return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -EINVAL); + return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm) ? 0 : -1); } int tonga_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) @@ -5826,7 +5832,7 @@ static int tonga_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_ if (phm_is_hw_access_blocked(hwmgr)) return 0; - return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -EINVAL); + return (0 == smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanRpmMax, us_max_fan_pwm) ? 0 : -1); } uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr) @@ -5962,7 +5968,7 @@ int tonga_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_st const struct tonga_power_state *psb = cast_const_phw_tonga_power_state(pstate2); int i; - if (pstate1 == NULL || pstate2 == NULL || equal == NULL) + if (equal == NULL || psa == NULL || psb == NULL) return -EINVAL; /* If the two states don't even have the same number of performance levels they cannot be the same state. */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index ae216fe8547d..34f4bef3691f 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c @@ -168,7 +168,7 @@ static int get_vddc_lookup_table( kzalloc(table_size, GFP_KERNEL); if (NULL == table) - return -1; + return -ENOMEM; memset(table, 0x00, table_size); @@ -206,7 +206,7 @@ static int get_platform_power_management_table( (struct phm_ppt_v1_information *)(hwmgr->pptable); if (NULL == ptr) - return -1; + return -ENOMEM; ptr->ppm_design = atom_ppm_table->ucPpmDesign; @@ -327,7 +327,7 @@ static int get_valid_clk( table = (struct phm_clock_array *)kzalloc(table_size, GFP_KERNEL); if (NULL == table) - return -1; + return -ENOMEM; memset(table, 0x00, table_size); @@ -378,7 +378,7 @@ static int get_mclk_voltage_dependency_table( kzalloc(table_size, GFP_KERNEL); if (NULL == mclk_table) - return -1; + return -ENOMEM; memset(mclk_table, 0x00, table_size); @@ -421,7 +421,7 @@ static int get_sclk_voltage_dependency_table( kzalloc(table_size, GFP_KERNEL); if (NULL == sclk_table) - return -1; + return -ENOMEM; memset(sclk_table, 0x00, table_size); @@ -464,7 +464,7 @@ static int get_pcie_table( pcie_table = (phm_ppt_v1_pcie_table *)kzalloc(table_size, GFP_KERNEL); if (NULL == pcie_table) - return -1; + return -ENOMEM; memset(pcie_table, 0x00, table_size); @@ -506,14 +506,14 @@ static int get_cac_tdp_table( tdp_table = kzalloc(table_size, GFP_KERNEL); if (NULL == tdp_table) - return -1; + return -ENOMEM; memset(tdp_table, 0x00, table_size); hwmgr->dyn_state.cac_dtp_table = kzalloc(table_size, GFP_KERNEL); if (NULL == hwmgr->dyn_state.cac_dtp_table) - return -1; + return -ENOMEM; memset(hwmgr->dyn_state.cac_dtp_table, 0x00, table_size); @@ -614,7 +614,7 @@ static int get_mm_clock_voltage_table( kzalloc(table_size, GFP_KERNEL); if (NULL == mm_table) - return -1; + return -ENOMEM; memset(mm_table, 0x00, table_size); @@ -943,7 +943,7 @@ int tonga_pp_tables_initialize(struct pp_hwmgr *hwmgr) hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL); PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), - "Failed to allocate hwmgr->pptable!", return -1); + "Failed to allocate hwmgr->pptable!", return -ENOMEM); memset(hwmgr->pptable, 0x00, sizeof(struct phm_ppt_v1_information)); diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c index 21c31db0df26..cdbb9f89bf36 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c @@ -1033,7 +1033,7 @@ int fiji_smum_init(struct pp_smumgr *smumgr) fiji_smu = kzalloc(sizeof(struct fiji_smumgr), GFP_KERNEL); if (fiji_smu == NULL) - return -1; + return -ENOMEM; smumgr->backend = fiji_smu; smumgr->smumgr_funcs = &fiji_smu_funcs; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c index 62ff76010aa6..d166fd925dbb 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c @@ -810,7 +810,7 @@ int tonga_smum_init(struct pp_smumgr *smumgr) tonga_smu = kzalloc(sizeof(struct tonga_smumgr), GFP_KERNEL); if (tonga_smu == NULL) - return -1; + return -ENOMEM; smumgr->backend = tonga_smu; smumgr->smumgr_funcs = &tonga_smu_funcs; -- 2.30.2