From c55fbcb8cf6b3653103f046232ada503e482b57d Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Mon, 12 Mar 2018 13:25:40 +0800 Subject: [PATCH] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate Add two properties of ref_clk and coefficient used by U2 slew rate calibrate which may vary on different SoCs Signed-off-by: Chunfeng Yun Reviewed-by: Matthias Brugger Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 41e09ed2ca70..0d34b2b4a6b7 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -27,6 +27,10 @@ Optional properties (controller (parent) node): - reg : offset and length of register shared by multiple ports, exclude port's private register. It is needed on mt2701 and mt8173, but not on mt2712. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process Required properties (port (child) node): - reg : address and length of the register set for the port. -- 2.30.2