From e466c2935fe196f4c9d512650f1224f194a00b51 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 8 Dec 2017 17:02:24 -0500 Subject: [PATCH] drm/amdgpu: remove some old gc 9.x registers MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Leftover from bring up. Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 8 ++-- .../amd/include/asic_reg/gc/gc_9_0_default.h | 7 --- .../amd/include/asic_reg/gc/gc_9_0_offset.h | 14 ------ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 45 ------------------- .../amd/include/asic_reg/gc/gc_9_1_offset.h | 14 ------ 5 files changed, 4 insertions(+), 84 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h index 003a131bad47..567a904804bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h +++ b/drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h @@ -48,7 +48,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_1[] = 0x00000000, // DB_STENCIL_WRITE_BASE 0x00000000, // DB_STENCIL_WRITE_BASE_HI 0x00000000, // DB_DFSM_CONTROL - 0x00000000, // DB_RENDER_FILTER + 0, // HOLE 0x00000000, // DB_Z_INFO2 0x00000000, // DB_STENCIL_INFO2 0, // HOLE @@ -259,8 +259,8 @@ static const unsigned int gfx9_SECT_CONTEXT_def_2[] = 0x00000000, // PA_SC_RIGHT_VERT_GRID 0x00000000, // PA_SC_LEFT_VERT_GRID 0x00000000, // PA_SC_HORIZ_GRID - 0x00000000, // PA_SC_FOV_WINDOW_LR - 0x00000000, // PA_SC_FOV_WINDOW_TB + 0, // HOLE + 0, // HOLE 0, // HOLE 0, // HOLE 0, // HOLE @@ -701,7 +701,7 @@ static const unsigned int gfx9_SECT_CONTEXT_def_7[] = { 0x00000000, // VGT_GS_MAX_PRIMS_PER_SUBGROUP 0x00000000, // VGT_DRAW_PAYLOAD_CNTL - 0x00000000, // VGT_INDEX_PAYLOAD_CNTL + 0, // HOLE 0x00000000, // VGT_INSTANCE_STEP_RATE_0 0x00000000, // VGT_INSTANCE_STEP_RATE_1 0, // HOLE diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h index 663d3af35baf..5bf84c6d0ec3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_default.h @@ -436,7 +436,6 @@ #define mmTA_CNTL_DEFAULT 0x8004d850 #define mmTA_CNTL_AUX_DEFAULT 0x00000000 #define mmTA_RESERVED_010C_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_DEFAULT 0x40000040 #define mmTA_STATUS_DEFAULT 0x00000000 #define mmTA_SCRATCH_DEFAULT 0x00000000 @@ -1700,7 +1699,6 @@ #define mmDB_STENCIL_WRITE_BASE_DEFAULT 0x00000000 #define mmDB_STENCIL_WRITE_BASE_HI_DEFAULT 0x00000000 #define mmDB_DFSM_CONTROL_DEFAULT 0x00000000 -#define mmDB_RENDER_FILTER_DEFAULT 0x00000000 #define mmDB_Z_INFO2_DEFAULT 0x00000000 #define mmDB_STENCIL_INFO2_DEFAULT 0x00000000 #define mmTA_BC_BASE_ADDR_DEFAULT 0x00000000 @@ -1806,8 +1804,6 @@ #define mmPA_SC_RIGHT_VERT_GRID_DEFAULT 0x00000000 #define mmPA_SC_LEFT_VERT_GRID_DEFAULT 0x00000000 #define mmPA_SC_HORIZ_GRID_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_LR_DEFAULT 0x00000000 -#define mmPA_SC_FOV_WINDOW_TB_DEFAULT 0x00000000 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_DEFAULT 0x00000000 #define mmCB_BLEND_RED_DEFAULT 0x00000000 #define mmCB_BLEND_GREEN_DEFAULT 0x00000000 @@ -2072,7 +2068,6 @@ #define mmVGT_EVENT_INITIATOR_DEFAULT 0x00000000 #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_DEFAULT 0x00000000 #define mmVGT_DRAW_PAYLOAD_CNTL_DEFAULT 0x00000000 -#define mmVGT_INDEX_PAYLOAD_CNTL_DEFAULT 0x00000000 #define mmVGT_INSTANCE_STEP_RATE_0_DEFAULT 0x00000000 #define mmVGT_INSTANCE_STEP_RATE_1_DEFAULT 0x00000000 #define mmVGT_ESGS_RING_ITEMSIZE_DEFAULT 0x00000000 @@ -2490,7 +2485,6 @@ #define mmWD_INDEX_BUF_BASE_DEFAULT 0x00000000 #define mmWD_INDEX_BUF_BASE_HI_DEFAULT 0x00000000 #define mmIA_MULTI_VGT_PARAM_DEFAULT 0x006000ff -#define mmVGT_OBJECT_ID_DEFAULT 0x00000000 #define mmVGT_INSTANCE_BASE_ID_DEFAULT 0x00000000 #define mmPA_SU_LINE_STIPPLE_VALUE_DEFAULT 0x00000000 #define mmPA_SC_LINE_STIPPLE_STATE_DEFAULT 0x00000000 @@ -2534,7 +2528,6 @@ #define mmSQC_WRITEBACK_DEFAULT 0x00000000 #define mmTA_CS_BC_BASE_ADDR_DEFAULT 0x00000000 #define mmTA_CS_BC_BASE_ADDR_HI_DEFAULT 0x00000000 -#define mmTA_GRAD_ADJ_UCONFIG_DEFAULT 0x40000040 #define mmDB_OCCLUSION_COUNT0_LOW_DEFAULT 0x00000000 #define mmDB_OCCLUSION_COUNT0_HI_DEFAULT 0x00000000 #define mmDB_OCCLUSION_COUNT1_LOW_DEFAULT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index e6d6171aa8b9..4ce090db7ef7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -841,8 +841,6 @@ #define mmTA_CNTL_AUX_BASE_IDX 0 #define mmTA_RESERVED_010C 0x0543 #define mmTA_RESERVED_010C_BASE_IDX 0 -#define mmTA_GRAD_ADJ 0x0544 -#define mmTA_GRAD_ADJ_BASE_IDX 0 #define mmTA_STATUS 0x0548 #define mmTA_STATUS_BASE_IDX 0 #define mmTA_SCRATCH 0x0564 @@ -3330,8 +3328,6 @@ #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 #define mmDB_DFSM_CONTROL 0x0018 #define mmDB_DFSM_CONTROL_BASE_IDX 1 -#define mmDB_RENDER_FILTER 0x0019 -#define mmDB_RENDER_FILTER_BASE_IDX 1 #define mmDB_Z_INFO2 0x001a #define mmDB_Z_INFO2_BASE_IDX 1 #define mmDB_STENCIL_INFO2 0x001b @@ -3542,10 +3538,6 @@ #define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 #define mmPA_SC_HORIZ_GRID 0x00ea #define mmPA_SC_HORIZ_GRID_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_LR 0x00eb -#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_TB 0x00ec -#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1 #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 #define mmCB_BLEND_RED 0x0105 @@ -4074,8 +4066,6 @@ #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 #define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 -#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7 -#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 @@ -4908,8 +4898,6 @@ #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 #define mmIA_MULTI_VGT_PARAM 0x2258 #define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 -#define mmVGT_OBJECT_ID 0x2259 -#define mmVGT_OBJECT_ID_BASE_IDX 1 #define mmVGT_INSTANCE_BASE_ID 0x225a #define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 #define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 @@ -4996,8 +4984,6 @@ #define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 #define mmTA_CS_BC_BASE_ADDR_HI 0x2381 #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 -#define mmTA_GRAD_ADJ_UCONFIG 0x2382 -#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_HI 0x23c1 diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 5c5e9b445432..2e1214be67a2 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -4576,15 +4576,6 @@ //TA_RESERVED_010C #define TA_RESERVED_010C__Unused__SHIFT 0x0 #define TA_RESERVED_010C__Unused_MASK 0xFFFFFFFFL -//TA_GRAD_ADJ -#define TA_GRAD_ADJ__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ__GRAD_ADJ_3_MASK 0xFF000000L //TA_STATUS #define TA_STATUS__FG_PFIFO_EMPTYB__SHIFT 0xc #define TA_STATUS__FG_LFIFO_EMPTYB__SHIFT 0xd @@ -14459,9 +14450,6 @@ #define DB_DFSM_CONTROL__PUNCHOUT_MODE_MASK 0x00000003L #define DB_DFSM_CONTROL__POPS_DRAIN_PS_ON_OVERLAP_MASK 0x00000004L #define DB_DFSM_CONTROL__DISALLOW_OVERFLOW_MASK 0x00000008L -//DB_RENDER_FILTER -#define DB_RENDER_FILTER__PS_INVOKE_MASK__SHIFT 0x0 -#define DB_RENDER_FILTER__PS_INVOKE_MASK_MASK 0x0000FFFFL //DB_Z_INFO2 #define DB_Z_INFO2__EPITCH__SHIFT 0x0 #define DB_Z_INFO2__EPITCH_MASK 0x0000FFFFL @@ -14959,11 +14947,9 @@ #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE__SHIFT 0x0 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE__SHIFT 0x1 #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE__SHIFT 0x5 -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING__SHIFT 0x8 #define PA_SC_TILE_STEERING_OVERRIDE__ENABLE_MASK 0x00000001L #define PA_SC_TILE_STEERING_OVERRIDE__NUM_SE_MASK 0x00000006L #define PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SE_MASK 0x00000060L -#define PA_SC_TILE_STEERING_OVERRIDE__DISABLE_SRBSL_DB_OPTIMIZED_PACKING_MASK 0x00000100L //CP_PERFMON_CNTX_CNTL #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE__SHIFT 0x1f #define CP_PERFMON_CNTX_CNTL__PERFMON_ENABLE_MASK 0x80000000L @@ -15003,20 +14989,6 @@ #define PA_SC_HORIZ_GRID__TOP_HALF_MASK 0x0000FF00L #define PA_SC_HORIZ_GRID__BOT_HALF_MASK 0x00FF0000L #define PA_SC_HORIZ_GRID__BOT_QTR_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_LR -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT__SHIFT 0x10 -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT__SHIFT 0x18 -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_LEFT_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_LR__LEFT_EYE_FOV_RIGHT_MASK 0x0000FF00L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_LEFT_MASK 0x00FF0000L -#define PA_SC_FOV_WINDOW_LR__RIGHT_EYE_FOV_RIGHT_MASK 0xFF000000L -//PA_SC_FOV_WINDOW_TB -#define PA_SC_FOV_WINDOW_TB__FOV_TOP__SHIFT 0x0 -#define PA_SC_FOV_WINDOW_TB__FOV_BOT__SHIFT 0x8 -#define PA_SC_FOV_WINDOW_TB__FOV_TOP_MASK 0x000000FFL -#define PA_SC_FOV_WINDOW_TB__FOV_BOT_MASK 0x0000FF00L //VGT_MULTI_PRIM_IB_RESET_INDX #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX__SHIFT 0x0 #define VGT_MULTI_PRIM_IB_RESET_INDX__RESET_INDX_MASK 0xFFFFFFFFL @@ -17010,13 +16982,11 @@ #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE__SHIFT 0x2 #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE__SHIFT 0x3 #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE__SHIFT 0x4 -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE__SHIFT 0x5 #define PA_SU_SMALL_PRIM_FILTER_CNTL__SMALL_PRIM_FILTER_ENABLE_MASK 0x00000001L #define PA_SU_SMALL_PRIM_FILTER_CNTL__TRIANGLE_FILTER_DISABLE_MASK 0x00000002L #define PA_SU_SMALL_PRIM_FILTER_CNTL__LINE_FILTER_DISABLE_MASK 0x00000004L #define PA_SU_SMALL_PRIM_FILTER_CNTL__POINT_FILTER_DISABLE_MASK 0x00000008L #define PA_SU_SMALL_PRIM_FILTER_CNTL__RECTANGLE_FILTER_DISABLE_MASK 0x00000010L -#define PA_SU_SMALL_PRIM_FILTER_CNTL__SRBSL_ENABLE_MASK 0x00000020L //PA_CL_OBJPRIM_ID_CNTL #define PA_CL_OBJPRIM_ID_CNTL__OBJ_ID_SEL__SHIFT 0x0 #define PA_CL_OBJPRIM_ID_CNTL__ADD_PIPED_PRIM_ID__SHIFT 0x1 @@ -17345,9 +17315,6 @@ #define VGT_DRAW_PAYLOAD_CNTL__EN_REG_RT_INDEX_MASK 0x00000002L #define VGT_DRAW_PAYLOAD_CNTL__EN_PIPELINE_PRIMID_MASK 0x00000004L #define VGT_DRAW_PAYLOAD_CNTL__OBJECT_ID_INST_EN_MASK 0x00000008L -//VGT_INDEX_PAYLOAD_CNTL -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN__SHIFT 0x0 -#define VGT_INDEX_PAYLOAD_CNTL__COMPOUND_INDEX_EN_MASK 0x00000001L //VGT_INSTANCE_STEP_RATE_0 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE__SHIFT 0x0 #define VGT_INSTANCE_STEP_RATE_0__STEP_RATE_MASK 0xFFFFFFFFL @@ -19849,9 +19816,6 @@ #define IA_MULTI_VGT_PARAM__EN_INST_OPT_BASIC_MASK 0x00200000L #define IA_MULTI_VGT_PARAM__EN_INST_OPT_ADV_MASK 0x00400000L #define IA_MULTI_VGT_PARAM__HW_USE_ONLY_MASK 0x00800000L -//VGT_OBJECT_ID -#define VGT_OBJECT_ID__REG_OBJ_ID__SHIFT 0x0 -#define VGT_OBJECT_ID__REG_OBJ_ID_MASK 0xFFFFFFFFL //VGT_INSTANCE_BASE_ID #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID__SHIFT 0x0 #define VGT_INSTANCE_BASE_ID__INSTANCE_BASE_ID_MASK 0xFFFFFFFFL @@ -20067,15 +20031,6 @@ //TA_CS_BC_BASE_ADDR_HI #define TA_CS_BC_BASE_ADDR_HI__ADDRESS__SHIFT 0x0 #define TA_CS_BC_BASE_ADDR_HI__ADDRESS_MASK 0x000000FFL -//TA_GRAD_ADJ_UCONFIG -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0__SHIFT 0x0 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1__SHIFT 0x8 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2__SHIFT 0x10 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3__SHIFT 0x18 -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_0_MASK 0x000000FFL -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_1_MASK 0x0000FF00L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_2_MASK 0x00FF0000L -#define TA_GRAD_ADJ_UCONFIG__GRAD_ADJ_3_MASK 0xFF000000L //DB_OCCLUSION_COUNT0_LOW #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW__SHIFT 0x0 #define DB_OCCLUSION_COUNT0_LOW__COUNT_LOW_MASK 0xFFFFFFFFL diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h index db7ef5ede0e5..030e0020902b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_offset.h @@ -815,8 +815,6 @@ #define mmTA_CNTL_AUX_BASE_IDX 0 #define mmTA_RESERVED_010C 0x0543 #define mmTA_RESERVED_010C_BASE_IDX 0 -#define mmTA_GRAD_ADJ 0x0544 -#define mmTA_GRAD_ADJ_BASE_IDX 0 #define mmTA_STATUS 0x0548 #define mmTA_STATUS_BASE_IDX 0 #define mmTA_SCRATCH 0x0564 @@ -3617,8 +3615,6 @@ #define mmDB_STENCIL_WRITE_BASE_HI_BASE_IDX 1 #define mmDB_DFSM_CONTROL 0x0018 #define mmDB_DFSM_CONTROL_BASE_IDX 1 -#define mmDB_RENDER_FILTER 0x0019 -#define mmDB_RENDER_FILTER_BASE_IDX 1 #define mmDB_Z_INFO2 0x001a #define mmDB_Z_INFO2_BASE_IDX 1 #define mmDB_STENCIL_INFO2 0x001b @@ -3829,10 +3825,6 @@ #define mmPA_SC_LEFT_VERT_GRID_BASE_IDX 1 #define mmPA_SC_HORIZ_GRID 0x00ea #define mmPA_SC_HORIZ_GRID_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_LR 0x00eb -#define mmPA_SC_FOV_WINDOW_LR_BASE_IDX 1 -#define mmPA_SC_FOV_WINDOW_TB 0x00ec -#define mmPA_SC_FOV_WINDOW_TB_BASE_IDX 1 #define mmVGT_MULTI_PRIM_IB_RESET_INDX 0x0103 #define mmVGT_MULTI_PRIM_IB_RESET_INDX_BASE_IDX 1 #define mmCB_BLEND_RED 0x0105 @@ -4361,8 +4353,6 @@ #define mmVGT_GS_MAX_PRIMS_PER_SUBGROUP_BASE_IDX 1 #define mmVGT_DRAW_PAYLOAD_CNTL 0x02a6 #define mmVGT_DRAW_PAYLOAD_CNTL_BASE_IDX 1 -#define mmVGT_INDEX_PAYLOAD_CNTL 0x02a7 -#define mmVGT_INDEX_PAYLOAD_CNTL_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_0 0x02a8 #define mmVGT_INSTANCE_STEP_RATE_0_BASE_IDX 1 #define mmVGT_INSTANCE_STEP_RATE_1 0x02a9 @@ -5195,8 +5185,6 @@ #define mmWD_INDEX_BUF_BASE_HI_BASE_IDX 1 #define mmIA_MULTI_VGT_PARAM 0x2258 #define mmIA_MULTI_VGT_PARAM_BASE_IDX 1 -#define mmVGT_OBJECT_ID 0x2259 -#define mmVGT_OBJECT_ID_BASE_IDX 1 #define mmVGT_INSTANCE_BASE_ID 0x225a #define mmVGT_INSTANCE_BASE_ID_BASE_IDX 1 #define mmPA_SU_LINE_STIPPLE_VALUE 0x2280 @@ -5283,8 +5271,6 @@ #define mmTA_CS_BC_BASE_ADDR_BASE_IDX 1 #define mmTA_CS_BC_BASE_ADDR_HI 0x2381 #define mmTA_CS_BC_BASE_ADDR_HI_BASE_IDX 1 -#define mmTA_GRAD_ADJ_UCONFIG 0x2382 -#define mmTA_GRAD_ADJ_UCONFIG_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_LOW 0x23c0 #define mmDB_OCCLUSION_COUNT0_LOW_BASE_IDX 1 #define mmDB_OCCLUSION_COUNT0_HI 0x23c1 -- 2.30.2