From f7346ef14cc5de19ee503da4b9df384999a79ea1 Mon Sep 17 00:00:00 2001
From: Manish Narani <manish.narani@xilinx.com>
Date: Mon, 27 Mar 2017 17:47:00 +0530
Subject: [PATCH] arm64: zynqmp: Enabled CCI support for USB

This patch adds CCI support for USB when CCI is enabled in design.
This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg'
property is added in order to modify a register in that to enable
coherency in Hardware.

Also add address to unit name to avoid dtc warning

Signed-off-by: Manish Narani <mnarani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
 arch/arm/dts/zynqmp.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index dce5da4e06..7def14d95a 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -1011,11 +1011,12 @@
 			power-domains = <&pd_uart1>;
 		};
 
-		usb0: usb0 {
+		usb0: usb0@ff9d0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
 			compatible = "xlnx,zynqmp-dwc3";
+			reg = <0x0 0xff9d0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
 			clocks = <&clk125>, <&clk125>;
 			#stream-id-cells = <1>;
@@ -1033,14 +1034,16 @@
 				interrupts = <0 65 4>;
 				/* snps,quirk-frame-length-adjustment = <0x20>; */
 				snps,refclk_fladj;
+				/* dma-coherent; */
 			};
 		};
 
-		usb1: usb1 {
+		usb1: usb1@ff9e0000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
 			status = "disabled";
 			compatible = "xlnx,zynqmp-dwc3";
+			reg = <0x0 0xff9e0000 0x0 0x100>;
 			clock-names = "bus_clk", "ref_clk";
 			clocks = <&clk125>, <&clk125>;
 			#stream-id-cells = <1>;
@@ -1058,6 +1061,7 @@
 				interrupts = <0 70 4>;
 				/* snps,quirk-frame-length-adjustment = <0x20>; */
 				snps,refclk_fladj;
+				/* dma-coherent; */
 			};
 		};
 
-- 
2.30.2